Conference paper
Capacitor Mismatch Error Cancellation Technique for a Successive Approximation A/D Converter
In
Proc. Ieee International Symposium on Circuits and Systems, Vol. 2
—
1999, Volume 2, pp. 326-329
Abstract
An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in conversion time, the first-order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated opamp is explained.
SWITCAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under non-ideal conditions, including 1% 3 sigma nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB opamp gain, and 30 mV opamp offset.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 1999 |
| Pages: | 326-329 |
| Proceedings: | 1999 IEEE International Symposium on Circuits and Systems |
| ISBN: | 0780354710 and 9780780354715 |
| Types: | Conference paper |
| DOI: | 10.1109/ISCAS.1999.780725 |
