Conference paper
Time-Predictable Virtual Memory
Virtual memory is an important feature of modern computer architectures. For hard real-time systems, memory protection is a particularly interesting feature of virtual memory. However, current memory management units are not designed for time-predictability and therefore cannot be used in such systems.
This paper investigates the requirements on virtual memory from the perspective of hard real-time systems and presents the design of a time-predictable memory management unit. Our evaluation shows that the proposed design can be implemented efficiently. The design allows address translation and address range checking in constant time of two clock cycles on a cache miss.
This constant time is in strong contrast to the possible cost of a miss in a translation look-aside buffer in traditional virtual memory organizations. Compared to a platform without a memory management unit, these two additional clock cycles per cache miss introduce only a small performance overhead.
| Language: | English |
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| Publisher: | IEEE |
| Year: | 2016 |
| Pages: | 158-165 |
| Proceedings: | 19th International Symposium on Real-Time Distributed Computing for Novel Applications and SystemsIEEE International Symposium on Real-Time Distributed Computing |
| ISBN: | 1467390321 , 146739033x , 9781467390323 and 9781467390330 |
| ISSN: | 23755261 |
| Types: | Conference paper |
| DOI: | 10.1109/ISORC.2016.30 |
| ORCIDs: | Schoeberl, Martin |
Computer crashes Indexes Memory management Operating systems Organizations Real-time systems Timing address range checking address translation cache memory cache storage clock cycles computer architecture computer architectures hard real-time systems memory protection real-time systems time-predictable memory management unit time-predictable virtual memory translation look-aside buffer virtual storage
