Conference paper
Stack Caching Using Split Data Caches
In most embedded and general purpose architectures, stack data and non-stack data is cached together, meaning that writing to or loading from the stack may expel non-stack data from the data cache. Manipulation of the stack has a different memory access pattern than that of non-stack data, showing higher temporal and spatial locality.
We propose caching stack and non-stack data separately and develop four different stack caches that allow this separation without requiring compiler support. These are the simple, window, and prefilling with and without tag stack caches. The performance of the stack cache architectures was evaluated using the Simple Scalar toolset where the window and prefilling stack cache without tag resulted in an execution speedup of up to 3.5% for the MiBench benchmarks, executed on an out-of-order processor with the ARM instruction set.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2015 |
| Pages: | 66-73 |
| Proceedings: | 18th IEEE International Symposium on Real-time ComputingIEEE International Symposium on Real-Time Distributed Computing |
| ISBN: | 1467377090 , 1467377104 , 9781467377096 , 9781467377102 , 1479977098 and 9781479977096 |
| Types: | Conference paper |
| DOI: | 10.1109/ISORCW.2015.59 |
| ORCIDs: | Schoeberl, Martin |
ARM instruction set Benchmark testing Distributed databases Memory management MiBench benchmarks Multicore processing Real-time systems Registers cache memory cache storage general purpose architectures memory access pattern microprocessors nonstack data cache out-of-order processor simple Scalar toolset spatial locality split data caches stack cache architectures stack caching temporal locality
