Conference paper
Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor
According to the safety-critical Java specification, priority ceiling emulation is a requirement for implementations, as it has preferable properties, such as avoiding priority inversion and being deadlock free on uni-core systems. In this paper we explore our hardware supported implementation of priority ceiling emulation on the multicore Java optimized processor, and compare it to the existing hardware locks on the Java optimized processor.
We find that the additional overhead for priority ceiling emulation on a multicore processor is several times higher than simpler, non-premptive locks, mainly due to slow access to shared memory. We also find that PCE is mostly viable with large critical sections.
Language: | English |
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Publisher: | IEEE Press |
Year: | 2015 |
Pages: | 268-271 |
Proceedings: | 18th IEEE International Symposium on Real-time ComputingIEEE International Symposium on Real-Time Distributed Computing |
ISBN: | 1479987816 , 1479987824 , 9781479987818 and 9781479987825 |
ISSN: | 15550885 and 23755261 |
Types: | Conference paper |
DOI: | 10.1109/ISORC.2015.33 |
ORCIDs: | Strøm, Torur Biskopstø and Schoeberl, Martin |
Emulation Hardware Java Java chip-multiprocessor Monitoring Multicore processing PCE Protocols Real-time systems concurrency control deadlock free priority inversion hardware locks hardware supported implementation locking microprocessor chips multicore multicore Java optimized processor multicore processor multiprocessing systems nonpremptive locks priority ceiling emulation safety-critical Java specification safety-critical java safety-critical software shared memory unicore systems