Conference paper
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks.
The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit switching as found in FPGAs.
The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology.
| Language: | English |
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| Publisher: | IEEE Computer Society Press |
| Year: | 2008 |
| Pages: | 55-64 |
| Proceedings: | Second ACM/IEEE International Symposium on Networks-on-Chip |
| ISBN: | 0769530982 and 9780769530987 |
| Types: | Conference paper |
| DOI: | 10.1109/NOCS.2008.4492725 |
| ORCIDs: | Sparsø, Jens |
Application-specific CMOS technology Circuit topology Communication Energy consumption Energy efficiency FPGA Field programmable gate arrays IP-blocks Network topology Network-on-Chip Network-on-a-chip NoC routers Reconfigurable Switches Switching circuits System-on-Chip System-on-a-chip energy-efficient topology switches field programmable gate arrays logic design network topology network-on-chip network-on-chip architecture physical circuit-switching reconfigurable topology system-on-chip
