Conference paper
FPGA Based Acceleration of Decimal Operations
Field Programmable Gate-Arrays (FPGAs) can efficiently implement application specific processors in nonconventional number systems, such as the decimal (Binary- Coded Decimal, or BCD) number system required for accounting accuracy in financial applications. The main purpose of this work is to show that applications requiring several decimal (BCD) operations can be accelerated by a processor implemented on a FPGA board connected to the computer by a standard bus.
For the case of a telephone billing application, we demonstrate that even a basic implementation of the decimal processor on the FPGA, without an advanced input/output interface, can achieve a speed-up of about 10 over its execution on the CPU of the hosting computer.
Language: | English |
---|---|
Publisher: | IEEE |
Year: | 2011 |
Pages: | 146-151 |
Proceedings: | International Conference on ReConFigurable Computing and FPGA's 2011 |
ISBN: | 0769545513 , 1457717344 , 9780769545516 and 9781457717345 |
Types: | Conference paper |
DOI: | 10.1109/ReConFig.2011.39 |
ORCIDs: | Nannarelli, Alberto |
Acceleration Adders Benchmark testing Central Processing Unit FPGA based acceleration Field programmable gate arrays Hardware Program processors decimal arithmetic decimal number system decimal operations field programmable gate arrays field programmable gate-arrays financial applications invoicing telephone billing application