Conference paper
High-speed parallel forward error correction for optical transport networks
This paper presents a highly parallelized hardware implementation of the standard OTN Reed-Solomon Forward Error Correction algorithm. The proposed circuit is designed to meet the immense throughput required by OTN4, using commercially available FPGA technology.
Language: | English |
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Year: | 2010 |
Proceedings: | BONE-Celtic Tiger2 Summer School |
Types: | Conference paper |
ORCIDs: | Ruepp, Sarah Renée , Berger, Michael Stübert and Wessing, Henrik |