Conference paper
Embedded System Synthesis under Memory Constraints
Abstract
This paper presents a genetic algorithm to solve the system synthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, the algorithm takes into account the memory size of processors and the size of interface buffers of communication links, and in particular the complicated interplay of these.
The presented algorithm is implemented as part of the LY-COS cosynthesis system.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 1999 |
| Pages: | 188-192 |
| Proceedings: | 7th International Workshop on Hardware/Software Codesign |
| ISBN: | 1581131321 and 9781581131321 |
| ISSN: | 23783966 and 10926100 |
| Types: | Conference paper |
| DOI: | 10.1109/HSC.1999.777430 |
| ORCIDs: | Madsen, Jan |
