Conference paper
A new architecture for a single-chip multi-channel beamformer based on a standard FPGA
A new architecture for a compact medical ultrasound beamformer has been developed. Combination of novel and known principles has been utilized, leading to low processing power requirements and simple analog circuitry. Usage of a field programmable gate array (FPGA) for the digital signal processing provides programming flexibility.
First, sparse sample processing is performed by generating the in-phase and quadrature beamformed signals. Hereby only 512 samples are beamformed for each line in an image. That leads to a 15-fold decrease in the number of operations and enables the use of Delta-Sigma (ΔΣ) modulation analog-to-digital converters (ADC).
Second, simple second-order ΔΣ modulation ADC with classic topology is used. This allows for simple analog circuitry and a very compact design. Several tens of these together with the corresponding preamplifiers can be fitted together onto a single analog integrated circuit. Third, parameter driven delay generation is used, using 3 input parameters per line per channel for either linear array imaging or phased array imaging.
The delays are generated on the fly. The delay generation logic also determines the digital apodization by using 2 additional parameters. The control logic consists of few adders and counters and requires very limited resources. Fourth, the beamformer is fully programmable. Any channel can be set to use an arbitrary delay curve, and any number of these channels can be used together in an extendable modular multi-channel system.
A prototype of the digital logic is implemented using a Xilinx Virtex-E series FPGA. A 5 MHz center frequency is used along with an oversampling ratio of 14. The sampling clock frequency used is 140 MHz and the number of channels in a single Xilinx 1 million gate FPGA XCV600E is 32. The beamformer utilizes all of the BlockRAM of the device and 33% of its Core Logic Block (CLB) resources.
Both simulation results and processed echo data from a phantom are presented.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2001 |
| Pages: | 1529-1533 |
| Proceedings: | 2001 IEEE Ultrasonics Symposium |
| ISBN: | 0780371771 and 9780780371774 |
| Types: | Conference paper |
| DOI: | 10.1109/ULTSYM.2001.992011 |
| ORCIDs: | Tomov, Borislav Gueorguiev and Jensen, Jørgen Arendt |
ADC Biomedical imaging Circuits Delay Delta modulation Delta-Sigma modulation analog-to-digital conveners Field programmable analog arrays Field programmable gate arrays Frequency Logic Phased arrays Ultrasonic imaging Xilinx Virtex-E series FPGA architecture array signal processing biomedical electronics biomedical ultrasonics compact medical ultrasound beamformer control logic delay curve delay generation logic delta-sigma modulation digital apodization digital signal processing extendable modular multi-channel system field programmable gate array field programmable gate arrays in-phase beamformed signals linear array imaging low processing power requirements medical image processing oversampling ratio parameter driven delay generation phantom phased array imaging processed echo data programming flexibility quadrature beamformed signals sampling clock frequency simple analog circuitry simulation results single-chip multi-channel beamformer sparse sample processing standard FPGA ultrasonic arrays
