An offset-trimmable array of magnetic-field-sensitive MOS transistors (MAGFETs)

Magnetic-field sensors can be implemented by the use of a magnetic-field-sensitive MOSFET structure, commonly referred to as a MAGFET. The MAGFET is a split-drain MOSFET where the difference between the drain currents is dependent on the magnetic field applied to the MAGFET. Unfortunately, the sensitivity of the MAGFET is rather small and the inherent offset between the drain currents (at zero magnetic field) may well be of the same magnitude as the field-dependent current difference, even for fields of about 0.1 T.

Hence, it is often necessary to introduce some sort of offset compensation. In this paper we present a new combination of an offset compensating circuit and a MAGFET cascade circuit with increased sensitivity. The offset compensation utilizes a digitally trimmable current mirror implemented by a multiple-gate MOS transistor structure.

A prototype circuit has been fabricated in a 2.4 mu m n-well CMOS technology. The measured results show that the offset is reduced by more than one order of magnitude.