Conference paper
Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller
A Clock- and Data-Recovery (CDR) IC for a Physical Layer Controller in an Asynchronous Transfer Mode (ATM) system operating at a bit rate of 2.488 Gb/s is presented. The circuit was designed and fabricated in a 0.8 μm BiCMOS process featuring 13 GHz fT bipolar transistors. Clock-recovery is accomplished with a Phase-Locked Loop (PLL).
The PLL uses a Phase- and Frequency Detector (PFD) to increase the pull-in range. No external components are required. A novel Voltage Controlled Oscillator (VCO) generating both in-phase and quadrature clocks, required by the PFD, is presented. The CDR includes a 1:8 demultiplexer with bit-rotation.
Emitter Coupled Logic (ECL) is used in the PLL, data-regeneration and part of the demultiplexer, while the low-speed parts of the demultiplexer are implemented in dynamic CMOS using the True Single-Phased Clock (TSPC) approach
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 1996 |
| Pages: | 125-128 |
| Proceedings: | 1996 IEEE International Symposium on Circuits and Systems |
| Journal subtitle: | Connecting the World |
| ISBN: | 0780330730 and 9780780330733 |
| Types: | Conference paper |
| DOI: | 10.1109/ISCAS.1996.541949 |
