Conference paper
A simple clockless Network-on-Chip for a commercial audio DSP chip
We design a very small, packet-switched, clockless Network-on-Chip (NoC) as a replacement for the existing crossbar-based communication infrastructure in a commercial audio DSP chip. Both solutions are laid out in a 0.18 um process, and compared in terms of area, power consumption and routing complexity.
Even though the NoC turns out to be larger and more power consuming than the existing crossbar implementation, it still accounts for less than 1% of the total chip area and power consumption, and is justified by a long list of advantages: The NoC is modular, scalable, and in contrast to the existing crossbar, it allows all blocks to communicate.
The total wire length is decreased by 22% which eases the layout process and makes the design less prone to routing congestion. Not least, the communicating blocks are decoupled by means of the NoC, providing a Globally-Asynchronous, Locally-Synchronous (GALS) system where independent clocking of the individual blocks is enabled.
This study shows that NoCs are feasible even for small systems.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2006 |
| Pages: | 641-648 |
| Proceedings: | 9th Euromicro Conference on Digital System Design |
| ISBN: | 0769526098 , 150909444X , 150909444x , 9780769526096 and 9781509094448 |
| Types: | Conference paper |
| DOI: | 10.1109/DSD.2006.17 |
| ORCIDs: | Sparsø, Jens |
Bandwidth Clocks Digital signal processing chips Energy consumption Mathematical model Network-on-a-chip Postal services Routing Transistors Wire audio signal processing clockless network-on-chip commercial audio DSP chip crossbar implementation digital signal processing chips globally-asynchronous system locally-synchronous system network-on-chip power consumption routing complexity routing congestion
