Conference paper
Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip
In this paper we explore the design of an asynchronous router for a time-division-multiplexed (TDM) network-on-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either synchronous or mesochronous, but both approaches have their limitations: a globally synchronous NOC is no longer feasible in today's sub micron technologies and a mesochronous NOC requires special FIFO-based synchronizers in all input ports of all routers in order to accommodate for clock phase differences.
This adds hardware complexity and increases area and power consumption. We propose to use asynchronous routers in order to achieve a simpler, more robust and globally-asynchronous NOC, and this represents an unexplored point in the design space. The paper presents a range of alternative router designs.
All routers have been synthesized for a 65nm CMOS technology, and the paper reports post-layout figures for area, speed and energy and compares the asynchronous designs with an existing mesochronous clocked router. The results show that an asynchronous router is 2 times smaller, marginally slower and with roughly the same energy consumption, while offering a robust solution to the clock distribution problem.
The paper further explores "clock-gating" of the individual pipeline stages in the asynchronous routers, and shows that this can lead to significant power savings.
Language: | English |
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Publisher: | IEEE |
Year: | 2013 |
Pages: | 319-326 |
Proceedings: | 16th Euromicro Conference on Digital System Design (DSD 2013)Euromicro Conference on Digital System Design |
ISBN: | 0769550746 , 1479929786 , 1479929794 , 9780769550749 , 9781479929788 and 9781479929795 |
Types: | Conference paper |
DOI: | 10.1109/DSD.2013.40 |
ORCIDs: | Sparsø, Jens |
CMOS integrated circuits CMOS technology Clocks FIFO-based synchronizers Latches Nickel Pipelines Real-time systems Synchronization TDM-based NOC designs area consumption asynchronous circuits asynchronous design asynchronous routers asynchronous time-division-multiplexed network-on-chip circuit complexity clock distribution problem clock phase differences clock-gating energy consumption globally-asynchronous NOC hard real-time systems hardware complexity integrated circuit design mesochronous NOC multiprocessing systems multiprocessor platform network routing network-on-chip pipeline stages post-layout figures power consumption power savings real-time systems router designs submicron technologies time division multiplexing