Conference paper
An Implantable CMOS Amplifier for Nerve Signals
In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact on the amplifier input nodes.
The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 5 nV/√Hz.
The amplifier power consumption is 275 μW.
| Language: | English |
|---|---|
| Year: | 2001 |
| Pages: | 1183,1184,1185,1186 |
| Proceedings: | 2001 IEEE 8th International Conference on Electronics, Circuits and Systems |
| Journal subtitle: | Conference Proceedings |
| ISBN: | 0780370570 and 9780780370579 |
| Types: | Conference paper |
| DOI: | 10.1109/ICECS.2001.957427 |
0.5 micron 275 muW 3.6 kHz 80 dB Australia Bandwidth CMOS analogue integrated circuits CMRR Control systems Electrodes Implants Mars Mechanical sensors Muscles PSRR Prototypes Signal processing amplifiers bandwidth biomedical electronics continuous-time offset compensation equivalent input referred noise gain implantable CMOS amplifier nerve signal neurophysiology power consumption signal recovery strong inversion transistor weak inversion transistor
