Conference paper
A 0.2 V 0.44 µW 20 kHz Analog to Digital Σ∆ Modulator with 57 fJ/conversion FoM
This paper presents a 90 nm CMOS ΣΔ A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator.
The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 μW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB.
| Language: | English |
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| Publisher: | IEEE |
| Year: | 2006 |
| Pages: | 187-190 |
| Proceedings: | The 32nd European Solid-State Circuits Conference |
| ISBN: | 1424403022 , 1424403030 , 150909363x , 9781424403028 , 9781424403035 and 9781509093632 |
| ISSN: | 19308833 and 26431319 |
| Types: | Conference paper |
| DOI: | 10.1109/ESSCIR.2006.307562 |
0.2 V 0.44 muW 20 kHz 3.4 MHz 50 fJ 90 nm Bandwidth CMOS A/D modulator CMOS integrated circuits Digital modulation Dynamic range Frequency measurement Linearity Power measurement Sampling methods Signal generators Threshold voltage Voltage-controlled oscillators analog-digital modulator conversion FoM sigma-delta modulation sigma-delta modulator voltage-controlled oscillator voltage-controlled oscillators
