Conference paper
Parallelism and Scalability in an Image Processing Application
System-on-Chip Hardware, Department of Informatics and Mathematical Modeling, Technical University of Denmark1
Department of Informatics and Mathematical Modeling, Technical University of Denmark2
Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark3
The recent trends in processor architecture show that parallel processing is moving into new areas of computing in the form of many-core desktop processors and multi-processor system-on-chip. This means that parallel processing is required in application areas that traditionally have not used parallel programs.
This paper investigates parallelism and scalability of an embedded image processing application. The major challenges faced when parallelizing the application were to extract enough parallelism from the application and to reduce load imbalance. The application has limited immediately available parallelism.
It is difficult to further extract parallelism since the application has small data sets and parallelization overhead is relatively high. There is also a fair amount of load imbalance which is made worse by a non-uniform memory latency. Even so, we show that with some tuning relative speedups in excess of 9 on a 16 CPU system can be reached.
| Language: | English |
|---|---|
| Publisher: | Springer Berlin / Heidelberg |
| Year: | 2008 |
| Pages: | 158-169 |
| Proceedings: | 4th International Workshop on OpenMP |
| Series: | Lecture Notes in Computer Science |
| ISBN: | 354079560X , 354079560x , 3540795618 , 9783540795605 and 9783540795612 |
| ISSN: | 03029743 |
| Types: | Conference paper |
| DOI: | 10.1007/978-3-540-79561-2_14 |
| ORCIDs: | Stuart, Matthias Bo and Karlsson, Sven |
