Conference paper
Performance evaluation of a java chip-multiprocessor
Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-memory multiprocessor and consists of up to 8 Java Optimized Processor (JOP) cores, an arbitration control device, and a global shared memory.
All components are interconnected with a system-on-chip bus.
| Language: | English |
|---|---|
| Year: | 2008 |
| Pages: | 34-42 |
| Proceedings: | 2008 International Symposium on Industrial Embedded Systems (SIES) |
| ISBN: | 1424419948 , 1424419956 , 9781424419944 and 9781424419951 |
| Types: | Conference paper |
| DOI: | 10.1109/SIES.2008.4577678 |
Bandwidth Computer industry Data structures Embedded computing Embedded system Hardware Java Java chip-multiprocessor Java optimized processor cores JopCMP Multicore processing Multiprocessing systems System-on-a-chip chip multiprocessing design computationally intensive matrix multiplication data structures embedded systems field programmable gate arrays field-programmable gate array global shared memory hardware configuration instruction cache size memory bandwidth multicore system performance evaluation shared data structure shared memory systems symmetric shared-memory multiprocessor system-on-chip system-on-chip bus
