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10 items by relevance
1 Conference paper

A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit

Yan, Like; Wu, Binbin; Wen, Yuan; Zhang, Shaobin; Chen, Tianzhou

2010 10th Ieee International Conference on Computer and Information Technology — 2010, pp. 2897-2902

It’s a promising way to improve performance significantly by adding reconfigurable processing unit to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. The Reconfigurable Logic

Year: 2010

Language: English

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2 Conference paper

A reconfigurable floating-point FFT architecture

Chenlu Wu; Wei Cao; Xuegong Zhou; Lingli Wang; Fang Wang; Baodi Yuan

2013 Ieee 10th International Conference on Asic — 2013, pp. 1-4

A novel reconfigurable single-precision floating-point FFT architecture for accelerating scientific computing is proposed in this paper. This architecture implements reconfigurable point FFT. The fully pipelined computing unit is used to speed up the FFT operation. To deal with conflicting access to delay unit, the improved method is adopted for temporary data storage, which merely costs additional 0.1% of the total memory resources. Compared with conventional CSD multipliers based implementation, our design with RMCM reduces the number of adders by 33.3% and 64.1% for radix-23 a...

Year: 2013

Language: English

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3 Journal article

A reconfigurable processor architecture combining multi-core and reconfigurable processing units

Wu, Binbin; Yan, Like; Zhang, Shaobin; Chen, Tianzhou; Wen, Yuan

Telecommunication Systems — 2014, Volume 55, Issue 3, pp. 333-344

It’s a promising way to improve performance significantly by adding reconfigurable processing unit (RPU) to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. Reconfigurable logic is separated

Year: 2014

Language: English

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4 Journal article

A reconfigurable modular fault-tolerant hypercube architecture

Yang, C.S.; Zu, L.-P.; Wu, Y.N.

Ieee Transactions on Parallel and Distributed Systems — 1994, Volume 5, Issue 10, pp. 1018,1019,1020,1021,1022,1023,1024,1025,1026,1027,1028,1029,1030,1031,1032

We propose a new fault-tolerant design of a hypercube system. We first build the fault-tolerant modules (FTM's), then we interconnect these FTM's as the modular hypercube. Finally, we obtain our proposed system by augmenting links, called the spare-sharing links (SSL's), in the modular hypercube, which forms a ring connection in our architecture. The characteristic of our system is that the spare nodes in an FTM can be used as local spares to replace the faulty nodes in the FTM, or as remote spares to replace the faulty nodes in other FTM's via the spare-sharing links in the architecture. T...

Year: 1994

Language: English

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5 Conference paper

MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture

Wu, Kehuai; Kanstein, Andreas; Madsen, Jan; Berekovic, Mladen

Reconfigurable Computing: Architectures, Tools and Applications — 2007, pp. 26-38

The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP) to applications by means of a sparsely interconnected array of functional units and register files. As high-ILP

Year: 2007

Language: English

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6 Journal article

System architecture of an adaptive reconfigurable DSP computing engine

An-Yeu Wu; Liu, K.J. Ray; Raghupathy, A.

Ieee Transactions on Circuits and Systems for Video Technology — 1998, Volume 8, Issue 1, pp. 54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73

In this paper, we present the system architecture of an adaptive reconfigurable DSP computing engine for numerically intensive front-end audio/video communications. The proposed system is a massively parallel architecture that is capable of performing most low-level computationally intensive data

Year: 1998

Language: English

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7 Conference paper

Reconfigurable back propagation based neural network architecture

Wu, Gin-Der; Zhu, Zhen-Wei; Lin, Bo-Wei

2011 International Symposium on Integrated Circuits — 2011, pp. 67-70

Since the topology of neural networks is very crucial to the performance, the reconfigurable ability of the neural network hardware is very important. Therefore, this paper proposes an efficient architecture to implement the reconfigurable back propagation based neural network (BPNN). To further

Year: 2011

Language: English

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8 Conference paper

An Asynchronous Energy-Efficient CNN Accelerator with Reconfigurable Architecture

Weijia Chen; Hui Wu; Shaojun Wei; Anping He; Hong Chen

2018 Ieee Asian Solid-state Circuits Conference (a-sscc) — 2018, pp. 51-54

In this paper, we introduce an asynchronous energy-efficient convolutional neural network (CNN) accelerator with reconfigurable architecture including six computing cores, each of which contains 5x5 processing elements. With the dynamically reconfigurable architecture, the data path

Year: 2018

Language: English

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9 Conference paper

Design of A Reconfigurable Architecture for Discrete and Continuous Wavelet Transformsn

Sun, Kang; Pan, Xuezeng; Liu, Zugen; Wu, Tao

2006 International Conference on Communication Technology — 2006, pp. 1-4

for discrete and continuous wavelet transform based on lifting scheme and a reconfigurable architecture that includes reconfigurable lifting step arrays and reconfigurable address generator are proposed. In order to validate this architecture, an FPGA prototype is built to test the reconfiguration of 2-D

Year: 2006

Language: English

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10 Journal article

A reconfigurable boolean n-cube architecture under faults

Yang, C.S.; Wu, S.Y.; Hsieh, W.S.; Huang, K.C.

Microprocessing and Microprogramming — 1992, Volume 35, Issue 35, pp. 673-679

A reconfigurable modular Boolean n-cube (RMBn) is proposed in this paper. We embed spare elements, including nodes (processors), switches and links, into each module in order to reconfigure a failed system. The proposed scheme is constructed in two levels. The first level is to build

Year: 1992

Language: English

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