Conference paper
4 Gb/s two-level to 2 symbol/s four-level converter GaAs IC for semiconductor optical amplifier modulators
A design of a 50 Ω impedance matched two-to-four level converter GaAs IC for two-electrode semiconductor optical amplifier modulators is presented. Eye diagrams with good eye openings and 0.33 V spacing between adjacent logic levels are demonstrated for input bit rates up to 4 Gb/s. A novel differential super buffer output driver is applied and output reflection coefficients |S22| of less than -12 dB for frequencies less than 10 GHz are obtained
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 1993 |
| Pages: | 299-301 |
| Proceedings: | 15th Annual Gallium Arsenide Integrated Circuit Symposium |
| ISBN: | 0780313933 and 9780780313934 |
| Types: | Conference paper |
| DOI: | 10.1109/GAAS.1993.394447 |
4 Gbits/s 50 ohm ASIC Bit rate Driver circuits GaAs Gallium arsenide III-V semiconductor III-V semiconductors Impedance Logic Optical buffering Optical design Optical modulation Photonic integrated circuits QASK SCFL Semiconductor optical amplifiers application specific integrated circuits bipolar logic circuits buffer circuits demultiplexer design differential amplifiers differential super buffer output driver driver circuits encoder circuit principle full-custom gallium arsenide impedance matched impedance matching integrated optoelectronics modulation coding optical QPSK optical communication equipment optical modulation quadrature phase shift keying semiconductor optical amplifier modulators two-electrode two-to-four level converter
