Conference paper
A codesign case study: implementing arithmetic functions in FPGAs
Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware.
The conclusion is that by adding one relatively simple board containing two FPGAs in the prototype setup, the total computing time is reduced by 30%. The total amount of image data, in this case 300 Mbyte, which has to be transmitted via the network is reduced by a factor of two, and the required network bandwidth is reduced similarly
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 1996 |
| Pages: | 389-394 |
| Proceedings: | 1996 IEEE Symposium and Workshop on Engineering of Computer-Based Systems |
| ISBN: | 0818673559 and 9780818673559 |
| Types: | Conference paper |
| DOI: | 10.1109/ECBS.1996.494565 |
300 Mbyte Arithmetic Bandwidth Design methodology FPGA technology Field programmable gate arrays Hardware Image analysis Prototypes Software performance Software prototyping System performance arithmetic functions board circuit CAD codesign dedicated 3D image analysis prototype system digital arithmetic digital signal processing chips field programmable gate arrays image data image sequences integers network bandwidth software engineering system performance total computing time vector length calculation
