Conference paper
A Neuron- and a Synapse Chip for Artificial Neural Networks
A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors.
In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 × 4 matrix-vector multiplier has been fabricated in a standard 2.4 ¿m CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 ¿s and the weight matrix has a 10 bit resolution.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 1992 |
| Pages: | 213-216 |
| Proceedings: | 18th European Solid-State Circuits Conference |
| ISBN: | 8798423207 and 9788798423201 |
| Types: | Conference paper |
| DOI: | 10.1109/ESSCIRC.1992.5468235 |
ANN configuration Artificial neural networks Backpropagation algorithms Bipolar transistors CMOS chip set CMOS integrated circuits CMOS process Capacitors Computer networks Neurofeedback Neurons Testing Voltage artificial neural networks capacitors hardware implementations hyperbolic tangent activation functions matrix multiplication matrix-vector multiplier multiplying circuits neural chips neuron chip propagation time size 2.4 mum synapse chip word length 10 bit
