Conference paper
Design and Implementation of Real-Time Transactional Memory
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is also appealing for real-time systems. In this paper an implementation of real-time transactional memory (RTTM) in the context of a real-time Java chip-multiprocessor (CMP) is presented.
To provide a predictable and analyzable solution of transactional memory, the transaction buffer is organized fully associative. Evaluation in an FPGA shows that an associativity of up to 64-way is possible without degrading the overall system performance. The paper presents synthesis results for different RTTM configurations and different number of processor cores in the CMP system.
A CMP system with up to 8 processor cores with RTTM support is feasible in an Altera Cyclone-II FPGA.
| Language: | English |
|---|---|
| Year: | 2010 |
| Pages: | 279-284 |
| Proceedings: | 20th International Conference on Field Programmable Logic and Applications |
| ISBN: | 0769541798 , 1424478421 , 142447843X , 142447843x , 9780769541792 , 9781424478422 and 9781424478439 |
| ISSN: | 19461488 and 1946147x |
| Types: | Conference paper |
| DOI: | 10.1109/FPL.2010.64 |
| ORCIDs: | Schoeberl, Martin |
Clocks Context FPGA Field programmable gate arrays Hardware Instruction sets Java Java chip multiprocessor Real time systems buffer storage chip multiprocessor system logic design multiprocessing systems optimistic synchronization mechanism processor cores real-time system real-time systems real-time transactional memory synchronisation transaction buffer
