Conference paper
A Hardware Framework for on-Chip FPGA Acceleration
In
Proceedings of the 15th International Symposium on Integrated Circuits (isic 2016)
—
2016, pp. 1-4
Abstract
In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator.
Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2016 |
| Pages: | 1-4 |
| Proceedings: | 15th International Symposium on Integrated Circuits |
| ISBN: | 1467390186 , 1467390194 , 1467390208 , 9781467390187 , 9781467390194 and 9781467390200 |
| Types: | Conference paper |
| DOI: | 10.1109/ISICIR.2016.7829683 |
| ORCIDs: | Nannarelli, Alberto |
