Journal article
A 10-bit 100 MSamples/s BiCMOS D/A Converter
This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8 micron BiCMOS process and is designed to operate at a sampling rate of 100MSamples/s. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies.
The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current.
The DAC operates at 5V, and has a power consumption of 650mW. The area of the chip-core is 2.2mm by 2.2mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency of about one tenth of the sample frequency (which is 100MSamples/s) the measured SFDR is 50db, and at a generated frequency of about one third of the sample frequency the measured SFD is as high as 43dB.
The DAC is operating up to a sampling frequency of approximately 140MSamples/s. The DAC uses the hierarchical switching scheme and therefore the dynamic performance is not described well using the conventional glitch energy. A new energy measure that replaces the conventional glitch energy is therefore proposed.
This energy measure is especially useful during the design phase.
Language: | English |
---|---|
Publisher: | Kluwer Academic Publishers |
Year: | 1997 |
Pages: | 15-28 |
Journal subtitle: | An International Journal |
ISSN: | 15731979 and 09251030 |
Types: | Journal article |
DOI: | 10.1023/A:1013274700649 |
ORCIDs: | Jørgensen, Ivan Herald Holger |