Conference paper
Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support
The Multi-Core NoC is a 4 by 4 Mesh NoC targeted for Altera FPGAs. It implements a deflective routing policy and is used to connect sixteen NIOS II processors. Each NIOS II is connected to the NoC via an address-mapped Resource Network Interface. The Multi-Core NoC is implemented on four separate Altera Stratix II FPGA boards, each hosting a Quad-Core NoC, which operates on a local 50 MHz clock.
It has an onboard throughput of 650 Mbps (12.5 MFlit/s), and uses 28% of the LUs, 18% of the ALUTs, 22 % of the dedicated registers and 31% of the total memory blocks of a Stratix II FPGA. Asynchronous clock bridges, with a throughput of 50 Mbps (~1MFlit/s), are used for the inter-board communication.
Application programs use an MPI compatible Hardware Abstraction Layer (HAL) to communicate with the Resource Network Interface of the NoC. The RNI sets up message transfer, with a maximum length of 512 bytes, and sends flits with the size of 32 bit data plus 20 bit headers through the network. The MPI is the bottleneck of the system; it takes 46 us (43.4 kPackets/s) to send a minimum-sized packet through the protocol stack to a near neighbour and bounce it back to the original application.
The bounce-back time for a far neighbour is 56 us.
Language: | English |
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Year: | 2009 |
Pages: | 52-57 |
Types: | Conference paper |
DOI: | 10.1145/1667520.1667527 |
Altera Application-specific VLSI designs Architectures Buffering Buses and high-speed links Communication hardware, interfaces and storage Communications management Computer systems organization Contextual software domains Distributed architectures FPGA Hardware MPI MPSoC Message passing Network protocols Networks NoC Operating systems Software and its engineering Software organization and properties Very large scale integration design hardware platform multi-core plesiochronous