Conference paper
Decimal Engine for Energy-Efficient Multicore Processors
Prior work demonstrated the use of specialized processors, or accelerators, be energy-efficient for binary floatingpoint (BFP) division and square root, and for decimal floatingpoint (DFP) operations. In the dark silicon era, where not all the circuits on the die can be powered simultaneously, we propose a hybrid BFP/DFP engine to perform BFP division and DFP addition, multiplication and division.
The main purpose of this engine is to offload the binary floating-point units for this type of operations and reduce the latency for decimal operations, and power and temperature for the whole die.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2014 |
| Pages: | 1-6 |
| Proceedings: | 22nd IFIP/IEEE International Conference on Very Large Scale IntegrationIFIP/IEEE International Conference on Very Large Scale Integration |
| ISBN: | 1479937630 , 1479937657 , 1479937673 , 1479960160 , 1479960179 , 9781479937639 , 9781479937653 , 9781479937677 , 9781479960163 and 9781479960170 |
| ISSN: | 23248440 and 23248432 |
| Types: | Conference paper |
| DOI: | 10.1109/VLSI-SoC.2014.7004176 |
| ORCIDs: | Nannarelli, Alberto |
Clocks Engines Hardware Program processors Registers Silicon accelerators binary floating-point division dark silicon era decimal engine decimal floating-point operations energy conservation energy-efficient multicore processors floating point arithmetic hybrid BFP-DFP engine multicore system-on-chips multiprocessing systems square root system-on-chip
