Conference paper
Degrading Precision Arithmetic for Low Power Signal Processing
Sometimes reducing the power dissipation of resource constrained electronic systems, such as those built for deep-space probes or for wearable devices is a top priority. In signal processing, it is possible to have an acceptable quality of the signal even introducing some errors. In this work, we analyze two methods to degrade the precision of arithmetic operations in DSP to save power.
The first method is based on disabling the lower (least-significant) portion of the datapath by clock-gating and forcing zeros. The second method is based on lowering the supply voltage and re-designing the carry-chains in the datapath to adapt to the increased delays.
| Language: | English |
|---|---|
| Year: | 2010 |
| Pages: | 1163-1167 |
| Proceedings: | 44th Asilomar Conference on Signals, Systems and Computers |
| ISBN: | 1424497205 , 1424497213 , 1424497221 , 9781424497201 , 9781424497218 and 9781424497225 |
| ISSN: | 10586393 and 25762303 |
| Types: | Conference paper |
| DOI: | 10.1109/ACSSC.2010.5757713 |
| ORCIDs: | Nannarelli, Alberto |
Adders Clocks DSP Delay Digital signal processing Dynamic range Finite impulse response filter Power dissipation carry logic carry-chain re-design clock-gating clocks digital signal processing chips digital signal processing system low power signal processing low-power electronics power dissipation precision arithmetic resource constrained electronic system signal processing
