Conference paper
A heterogeneous multi-core platform for low power signal processing in systems-on-chip
In
Proceedings of the 28th European Solid-state Circuits Conference, 2002. Esscirc 2002
—
2002, pp. 73,74,75,76
Abstract
This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication is based on message passing.
The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more than 6-21 times lower than a general purpose CPU/DSP corewhile executing non-trivial industrial applications.
| Language: | English |
|---|---|
| Publisher: | IEEE Press |
| Year: | 2002 |
| Pages: | 73,74,75,76 |
| Proceedings: | 28th European Solid-State Circuits Conference |
| ISBN: | 8890084790 and 9788890084799 |
| Types: | Conference paper |
| ORCIDs: | Sparsø, Jens |
