Conference paper
Models of Communication for Multicore Processors
In
Proceedings of the 18th Ieee International Symposium on Real-time Distributed Computing (isorc 2015)
—
2015, pp. 44-51
Abstract
To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e.g., shared caches with cache coherency protocols, core-to-core networks-on-chip, and shared scratchpad memories.
In this paper we explore the different hardware mechanism for on-chip communication and how they support or favor different models of communication. Furthermore, we discuss the usability of the different models of communication for real-time systems.
| Language: | English |
|---|---|
| Publisher: | IEEE Press |
| Year: | 2015 |
| Pages: | 44-51 |
| Proceedings: | 18th IEEE International Symposium on Real-time ComputingIEEE International Symposium on Real-Time Distributed Computing |
| ISBN: | 1467377090 , 1467377104 , 9781467377096 and 9781467377102 |
| Types: | Conference paper |
| DOI: | 10.1109/ISORCW.2015.57 |
| ORCIDs: | Schoeberl, Martin and Sparsø, Jens |
