Conference paper
An Area-Efficient TDM NoC Supporting Reconfiguration for Mode Changes
This paper presents an area-efficient time-division-multiplexing (TDM) network-on-chip (NoC) intended for use in a multicore platform for hard real-time systems. In such a platform, a mode change at the application level requires the tear-down and set-up of some virtual circuits without affecting the virtual circuits that persist across the mode change.
Our NoC supports such reconfiguration in a very efficient way, using the same resources that are used for transmission of regular data. We evaluate the presented NoC in terms of worst-case reconfiguration time, hardware cost, and maximum operating frequency. The results show that the hardware cost for an FPGA implementation of our architecture is a factor of 2.2 to 3.9 times smaller than other NoCs with reconfiguration functionalities, and that the worst-case time for a reconfiguration is shorter or comparable to those NoCs.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2016 |
| Pages: | 1-4 |
| Proceedings: | 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)IEEE/ACM International Symposium on Networks-on-Chip |
| ISBN: | 1467390305 , 1467390313 , 9781467390309 and 9781467390316 |
| Types: | Conference paper |
| DOI: | 10.1109/NOCS.2016.7579324 |
| ORCIDs: | Pezzarossa, Luca and Sparsø, Jens |
FPGA implementation Hardware Nickel Pipeline processing Pipelines Program processors Schedules Time division multiplexing application level area-efficient TDM NoC field programmable gate arrays hard real-time systems hardware cost maximum operating frequency mode changes multicore platform multiprocessing systems network-on-chip real-time systems reconfiguration functionalities time division multiplexing time-division-multiplexing virtual circuits worst-case reconfiguration time
