Conference paper
Power Dissipation Challenges in Multicore Floating-Point Units
With increased densities on chips and the growing popularity of multicore processors and general-purpose graphics processing units (GPGPUs) power dissipation and energy consumption pose a serious challenge in the design of system-on-chips (SoCs) and a rise in costs for heat removal. In this work, we analyze the impact of power dissipation in floating-point (FP) units and we consider different alternatives in the implementation of FP-division that lead to substantial energy savings.
We compare the implementation of division in a Fused Multiply-Add (FMA) unit based on the Newton-Raphson approximation algorithm to the implementation in a dedicated digit-recurrence unit. The results show a significant reduction of energy in a typical scientific application when the division digit-recurrence unit is used.
In addition, we model the thermal behavior of the considered FP-units.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2010 |
| Pages: | 257-264 |
| Proceedings: | 21st IEEE International Conference on Application-specific Systems, Architectures and Processors |
| ISBN: | 1424469651 , 142446966X , 142446966x , 1424469678 , 9781424469659 , 9781424469666 and 9781424469673 |
| ISSN: | 10636268 |
| Types: | Conference paper |
| DOI: | 10.1109/ASAP.2010.5540986 |
| ORCIDs: | Nannarelli, Alberto |
Clocks Concurrent computing Cooling Costs Energy consumption Heat sinks Multicore processing Newton-Raphson approximation algorithm Newton-Raphson method Power dissipation System-on-a-chip Thermal management computer graphic equipment coprocessors digit recurrence unit division floating point arithmetic floating-point fused multiply-add fused multiply-add unit general purpose graphic processing unit low power multicore floating point unit multicore processor power dissipation system-on-chip thermal analysis
