Journal article
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation : Architecture, Configuration Algorithms, and Evaluation
Biomedical Engineering, Department of Electrical Engineering, Technical University of Denmark1
Department of Electrical Engineering, Technical University of Denmark2
Department of Informatics and Mathematical Modeling, Technical University of Denmark3
Computer Science and Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark4
This article presents a reconfigurable network-on-chip architecture called ReNoC, which is intended for use in general-purpose multiprocessor system-on-chip platforms, and which enables application-specific logical NoC topologies to be configured, thus providing both efficiency and flexibility. The article presents three novel algorithms that synthesize an application-specific NoC topology, map it onto the physical ReNoC architecture, and create deadlock-free, application-specific routing algorithms.
We apply our algorithms to a mixture of real and synthetic applications and target three different physical architectures. Compared to a conventional NoC, ReNoC reduces power consumption by up to 58% on average.
| Language: | English |
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| Publisher: | ACM, 2 Penn Plaza, Suite 701, New York, NY, USA |
| Year: | 2011 |
| Pages: | 1-26 |
| ISSN: | 15583465 and 15399087 |
| Types: | Journal article |
| DOI: | 10.1145/2043662.2043669 |
| ORCIDs: | Stuart, Matthias Bo and Sparsø, Jens |
Algorithms Configuration Experimentation Mapping Network-on-chip Performance Routing Synthesis System-on-chip
