Journal article
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing
This paper describes a low-power programmable DSP architecture that targets audio signal processing. The architecture can be characterized as a heterogeneous multiprocessor consisting of small instruction set processors called mini-cores as well as standard DSP and CPU cores that communicate using message passing.
The mini-cores are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occur at the sampling rate only.
| Language: | English |
|---|---|
| Publisher: | Kluwer Academic Publishers |
| Year: | 2004 |
| Pages: | 95-110 |
| ISSN: | 1573109x , 09225773 , 15730506 and 13875485 |
| Types: | Journal article |
| DOI: | 10.1023/B:VLSI.0000017005.01462.d5 |
| ORCIDs: | Sparsø, Jens |
ASIP—application specific instruction set processor Circuits and Systems Computer Imaging, Vision, Pattern Recognition and Graphics Electrical Engineering Engineering Image Processing and Computer Vision Pattern Recognition Signal, Image and Speech Processing audio signal processing heterogeneous low power multiprocessor scalable architecture
