Journal article
Verification of Chisel Hardware designs with ChiselVerify
Embedded Systems Engineering, Department of Applied Mathematics and Computer Science, Technical University of Denmark1
Department of Applied Mathematics and Computer Science, Technical University of Denmark2
University of California at Berkeley3
Tampere University4
Technical University of Denmark5
Department of Micro- and Nanotechnology, Technical University of Denmark6
With the current ever-increasing demand for performance, hardware developers find themselves turning ever-more towards the construction of application-specific accelerators to achieve higher performance and lower energy consumption. In order to meet the ever-shortening time constraints, both hardware development and verification tools need to be improved.
Chisel, as a hardware construction language, tackles this problem by speeding up the development of digital designs. However, the Chisel infrastructure lacks tools for verification. This paper improves the efficiency of verification in Chisel by proposing methods to support both formal and dynamic verification of digital designs in Scala.
It builds on top of ChiselTest, the official testing framework for Chisel. Our work supports functional coverage, constrained random verification, bus functional models, and transaction-level modeling in a verification library named ChiselVerify, while the formal methods are directly integrated into Chisel3.
Language: | English |
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Year: | 2023 |
Proceedings: | 2021 IEEE Nordic Circuits and Systems Conference |
ISSN: | 18729436 and 01419331 |
Types: | Journal article |
DOI: | 10.1016/j.micpro.2022.104737 |
ORCIDs: | Schoeberl, Martin and 0000-0001-9663-1672 |