Conference paper
A Light-Weight Statically Scheduled Network-on-Chip
Department of Informatics and Mathematical Modeling, Technical University of Denmark1
Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark2
Computer Science and Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark3
This paper investigates how a light-weight, statically scheduled network-on-chip (NoC) for real-time systems can be designed and implemented. The NoC provides communication channels between all cores with equal bandwidth and latency. The design is FPGA-friendly and consumes a minimum of resources. We implemented a 64 core 16-bit multiprocessor connected with the proposed NoC in a low-cost FPGA.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2012 |
| Pages: | 1-6 |
| Proceedings: | 2012 IEEE 30th NORCHIP ConferenceNORCHIP |
| ISBN: | 1467322210 , 1467322229 , 9781467322218 , 9781467322225 , 1467322237 and 9781467322232 |
| Types: | Conference paper |
| DOI: | 10.1109/NORCHP.2012.6403129 |
| ORCIDs: | Schoeberl, Martin and Sparsø, Jens |
Clocks FPGA Field programmable gate arrays Program processors Random access memory Registers Schedules Time division multiplexing communication channels field programmable gate arrays integrated circuit design logic design microprocessor chips multiprocessor network-on-chip real-time systems word length 16 bit
