Journal article
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization
With the continuing scaling of CMOS technology, on-chip temperature and thermal-induced variations have become a major design concern. To effectively limit the high temperature in a chip equipped with a cost-effective cooling system, thermal specific approaches, besides low power techniques, are necessary at the chip design level.
The high temperature in hotspots and large thermal gradients are caused by the high local power density and the nonuniform power dissipation across the chip. With the objective of reducing power density in hotspots, we propose two placement techniques that spread cells in hotspots over a larger area.
Increasing the area occupied by the hotspot directly reduces its power density, leading to a reduction in peak temperature and thermal gradient. To minimize the introduced overhead in delay and dynamic power, we maintain the relative positions of the coupling cells in the new layout. We compare the proposed methods in terms of temperature reduction, timing, and area overhead to the baseline method, which enlarges the circuit area uniformly.
The experimental results showed that our methods achieve a larger reduction in both peak temperature and thermal gradient than the baseline method. The baseline method, although reducing peak temperature in most cases, has little impact on thermal gradient.
Language: | English |
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Publisher: | IEEE |
Year: | 2013 |
Pages: | 406-418 |
ISSN: | 19374151 and 02780070 |
Types: | Journal article |
DOI: | 10.1109/TCAD.2012.2228267 |
ORCIDs: | Nannarelli, Alberto |
Area management Hotspot Layout Placement Power density SPICE Temperature reduction Thermal gradient Thermal modeling
CMOS integrated circuits CMOS technology Density measurement Heating Integrated circuit modeling Power demand Power system measurements Temperature sensors Thermal management continuing scaling coupling cells hotspot layout layout-driven post-placement techniques on-chip temperature placement power density system-on-chip temperature reduction thermal gradient thermal gradient minimization thermal modeling thermal-induced variations