Conference paper
A Variant of a Radix-10 Combinational Multiplier
In
2008 Ieee International Symposium on Circuits and Systems
—
2008, pp. 3370-3373
Abstract
We consider the problem of adding the partial products in the combinational decimal multiplier presented by Lang and Nannarelli. In the original paper this addition is done with a tree of decimal carry-save adders. In this paper, we treat the problem using the multi-operand decimal addition previously published by Dadda, where the sum of each column of the partial product array is obtained first in binary form and then converted to decimal.
The multiplication, using a 90 nm CMOS technology, in this modified scheme takes 2.51 ns, while in the original scheme it takes 2.65 ns. The area of the two schemes is roughly the same.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2008 |
| Pages: | 3370-3373 |
| Proceedings: | 2008 IEEE International Symposium on Circuits and Systems |
| ISBN: | 1424416833 , 1424416841 , 9781424416837 and 9781424416844 |
| ISSN: | 21581525 and 02714302 |
| Types: | Conference paper |
| DOI: | 10.1109/ISCAS.2008.4542181 |
| ORCIDs: | Nannarelli, Alberto |
Keywords
