Journal article ยท Ahead of Print article
Design-For-Testability of On-Chip Control in mVLSI Biochips
To enable mVLSI biochips for point-of-care applications, recent work has focused on reducing the number of off-chip pressure sources, using on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Since these on-chip pneumatic control logic circuits in turn control the fluidic operations, it is very important that they are fault-free, in order to avoid the failure of biochemical applications.
For the first time, this paper proposes a design-fortestability (DFT) scheme to test for faults inside on-chip pneumatic control logic circuits, by adding observation pneumatic latches into the circuit.
Language: | English |
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Publisher: | IEEE Computer Society |
Year: | 2019 |
Pages: | 48-56 |
ISSN: | 15581918 , 07407475 , 21682356 and 21682364 |
Types: | Journal article and Ahead of Print article |
DOI: | 10.1109/MDAT.2018.2873448 |
ORCIDs: | Pop, Paul and Madsen, Jan |
Biochips Circuit faults Logic circuits Logic gates Microfluidics Process control System-on-chip VLSI Valves bio-chip architectures design for testability design-for-testability graph theory integrated circuit testing lab-on-a-chip manufacturing defects microfluidic very large scale integration microfluidics on-chip control physical defects point-of-care systems