Journal article
Twelve-bit 20-GHz reduced size pipeline accumulator in 0.25 μm SiGe:C technology for direct digital synthesiser applications
Dept. of Electr. Eng., Tech. Univ. of Denmark, Lyngby, Denmark1
IHP Microelectron. GmbH, Frankfurt, Germany2
Terahertz Photonics, Johann Wolfgang Goethe Univ., Frankfurt, Germany3
This article presents a 20 GHz, 12-bit pipeline accumulator with a reduced number of registers, suitable for direct digital synthesiser (DDS) applications. The accumulator is implemented in the IHP SG25H1 (0.25 μm) SiGe:C technology featuring heterojunction bipolar transistors (HBTs) with Ft/Fmax of 180/220 GHz.
The accumulator architecture omits the pre-skewing registers of the pipeline, thereby lowering both power consumption and circuit complexity. Some limitations to this design are discussed and the necessary equations for determining the phase jump encountered each time the control word (synthesised frequency) is changed are presented.
For many applications employing signal processing after detection, this phase shift can then be corrected for. Compared to a full pipeline architecture (omitting the input circuitry for the most significant bit, as is customary for such designs), the implemented 12-bit accumulator reduces the number of registers by 55% and the power by approximately 32%, while obtaining the highest clock frequency for SiGe:C accumulators intended for DDS applications.
| Language: | English |
|---|---|
| Publisher: | IET |
| Year: | 2012 |
| Pages: | 19-27 |
| ISSN: | 17518598 and 1751858x |
| Types: | Journal article |
| DOI: | 10.1049/iet-cds.2010.0399 |
DDS applications Ge-Si alloys HBT SiGe:C carbon circuit complexity direct digital synthesis direct digital synthesiser applications frequency 20 GHz heterojunction bipolar transistors network synthesis pipeline accumulator pipelines power consumption signal processing size 0.25 mum word length 12 bit
