Journal article
Power Efficient Division and Square Root Unit
Department of Informatics and Mathematical Modeling, Technical University of Denmark1
Computer Science and Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark2
Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark3
Although division and square root are not frequent operations, most processors implement them in hardware to not compromise the overall performance. Two classes of algorithms implement division or square root: digit-recurrence and multiplicative (e.g., Newton-Raphson) algorithms. Previous work shows that division and square root units based on the digit-recurrence algorithm offer the best tradeoff delay-area-power.
Moreover, the two operations can be combined in a single unit. Here, we present a radix-16 combined division and square root unit obtained by overlapping two radix-4 stages. The proposed unit is compared to similar solutions based on the digit-recurrence algorithm and it is compared to a unit based on the multiplicative Newton-Raphson algorithm.
Language: | English |
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Publisher: | IEEE |
Year: | 2012 |
Pages: | 1059-1070 |
ISSN: | 15579956 , 00189340 and 23263814 |
Types: | Journal article |
DOI: | 10.1109/TC.2012.82 |
ORCIDs: | Nannarelli, Alberto |
Adders Convergence Hardware Multiplexing Newton-Raphson method Program processors Redundancy Registers digit recurrence algorithm digit-recurrence. division floating point arithmetic multiplicative Newton-Raphson algorithm power aware computing power efficiency square root square root unit