Conference paper
High-Level Design Flow for All-Digital PLLs
Deep-submicrometer CMOS processes are not suitable for traditional analog circuit design but they provide new opportunities of integrating complex digital functions. Within RF wireless communications, frequency synthesis stands out as a fundamental feature and novel digital solutions have been suggested for its implementation.
Moving from an existing model, the goal of this paper is to outline the steps of a high-level approach to the design of an all-digital phase-locked loop (ADPLL).
Language: | English |
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Year: | 2006 |
Pages: | 247-250 |
Proceedings: | 2006 IEEE 24th NORCHIP Conference |
ISBN: | 1424407729 and 9781424407729 |
Types: | Conference paper |
DOI: | 10.1109/NORCHP.2006.329221 |
Analog circuits CMOS process Circuit synthesis Frequency conversion Frequency synthesizers Phase locked loops RF wireless communications Radio frequency Semiconductor device modeling Time domain analysis Wireless communication all-digital PLL digital phase locked loops digital solutions frequency synthesis frequency synthesizers high level synthesis high-level design radiocommunication