Conference paper
Software-Defined GPS Receiver Implemented on the Parallella-16 Board
This paper describes a GPS software receiver design made of inexpensive and physically small hardware components. The small embedded platform, known as the Parallella-16 computer has been utilized in conjunction with a commercial RF front-end to construct a 4-channel real time software GPS receiver.
The Parallella-16 board is a kickstarter-funded platform consisting of a dual-core ARM A9 CPU, an integrated FPGA and a 16-core coprocessor known as the Epiphany. The main contribution in this paper has been the development of a GPS tracking algorithm, which utilizes the parallelism in the Epiphany processor.
The total cost of the hardware is below 150$ and the size is comparable to a credit-card. The receiver has been developed for research in GNSS/INS integration on small Unmanned Aerial Vehicles (UAVs).
| Language: | English |
|---|---|
| Publisher: | The Institute of Navigation |
| Year: | 2015 |
| Pages: | 3171-3177 |
| Proceedings: | 28th International Technical Meeting of The Satellite Division of the Institute of Navigation |
| Types: | Conference paper |
| ORCIDs: | Olesen, Daniel Madelung , Jakobsen, Jakob and Knudsen, Per |
