Conference paper
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have developed algorithms for process graph scheduling based on listscheduling and branch-and-bound strategies. One essential contribution is in the manner in which information on process allocation is used in order to efficiently derive a good quality or optimal schedule.
Experiments show the superiority of these algorithms compared to previous approaches like critical-path heuristics and ILP based optimal scheduling. An extension of our approach allows the scheduling of conditional process graphs capturing both data and control flow. In this case a schedule table has to be generated so that the worst case delay is minimized.
| Language: | English |
|---|---|
| Year: | 1998 |
| Pages: | 168-175 |
| Proceedings: | 24th EUROMICRO Conference |
| Series: | Euromicro Conference. Proceedings |
| ISBN: | 0818686464 and 9780818686467 |
| ISSN: | 23769505 and 10896503 |
| Types: | Conference paper |
| DOI: | 10.1109/EURMIC.1998.711792 |
| ORCIDs: | Pop, Paul |
ASICs Computer architecture Delay estimation Embedded computing Embedded system Hardware ILP based optimal scheduling Information science Optimal scheduling Processor scheduling Scheduling algorithm Software systems branch and bound strategies conditional process graphs critical path heuristics embedded systems hardware/software system synthesis high level synthesis list scheduling optimal schedule performance estimation process allocation process graph scheduling processor scheduling real-time systems resource allocation schedule table shared busses software engineering tree searching worst case delay
