Conference paper
Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications
Technical University of Denmark1
Department of Informatics and Mathematical Modeling, Technical University of Denmark2
Computer Science and Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark3
Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark4
Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation to the execution on a CPU.
The experimental results show that impressive results, in terms of speed-up and energy savings, can be obtained by using FPGA-based accelerators at expenses of a longer development time.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2012 |
| Pages: | 1-4 |
| Proceedings: | 2012 IEEE 30th NORCHIP ConferenceNORCHIP |
| ISBN: | 1467322210 , 1467322229 , 1467322237 , 9781467322218 , 9781467322225 and 9781467322232 |
| Types: | Conference paper |
| DOI: | 10.1109/NORCHP.2012.6403096 |
| ORCIDs: | Nannarelli, Alberto |
CPU Computational modeling Data models Europe European option pricing FPGA-based accelerator FPGA-based specific processor Field programmable gate arrays Mathematical model Monte Carlo methods Monte Carlo simulation Timing field programmable gate array field programmable gate arrays financial application financial data processing financial derivative calculation hardware accelerator logic design power dissipation power efficient FPGA
