Conference paper
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP) to applications by means of a sparsely interconnected array of functional units and register files. As high-ILP architectures achieve only low parallelism when executing partially sequential code segments, which is also known as Amdahl’s law, this paper proposes to extend ADRES to MT-ADRES (Multi-Threaded ADRES) to also exploit thread-level parallelism.
On MT-ADRES architectures, the array can be partitioned in multiple smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation that exploits a mix of thread-level parallelism and instruction-level parallelism.
Language: | English |
---|---|
Publisher: | Springer Berlin / Heidelberg |
Year: | 2007 |
Pages: | 26-38 |
Proceedings: | 3rd International Workshop on Applied Reconfigurable Computing |
Journal subtitle: | Lecture Notes in Computer Science |
ISBN: | 1280940700 , 3540714308 , 3540714316 , 9781280940705 , 9783540714309 and 9783540714316 |
Types: | Conference paper |
DOI: | 10.1007/978-3-540-71431-6 |
ORCIDs: | Madsen, Jan |