Conference paper
Experiences with Compiler Support for Processors with Exposed Pipelines
Department of Applied Mathematics and Computer Science, Technical University of Denmark1
Language-Based Technology, Department of Applied Mathematics and Computer Science, Technical University of Denmark2
Embedded Systems Engineering, Department of Applied Mathematics and Computer Science, Technical University of Denmark3
Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity.
However, it is not clear if current production compilers can successfully meet the strict constraints on instruction order and generate efficient object code. In this paper, we present our experiences developing a compiler backend using the GNU Compiler Collection, GCC. For a set of C benchmarks, we show that a Tinuso implementation with our GCC backend reaches a relative speedup of up to 1.73 over a similar Xilinx Micro Blaze configuration while using 30% fewer hardware resources.
While our experiences are generally positive, we expose some limitations in GCC that need to be addressed to achieve the full performance potential of Tinuso.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2015 |
| Pages: | 137-143 |
| Proceedings: | 29th IEEE International Parallel and Distributed Processing SymposiumIEEE International Parallel and Distributed Processing Symposium |
| ISBN: | 0769555101 , 1467376841 , 146737685X , 146737685x , 9780769555102 , 9781467376846 and 9781467376853 |
| Types: | Conference paper |
| DOI: | 10.1109/IPDPSW.2015.9 |
| ORCIDs: | Jensen, Nicklas Bo and Karlsson, Sven |
Benchmark testing C benchmarks C language Delays FPGA Field programmable gate arrays GCC backend GNU Compiler Collection Hardware Pipelines Program processors Registers Tinuso Xilinx MicroBlaze configuration compiler toolchain computing systems field programmable gate arrays hardware complexity hardware resources instruction order object code generation pipeline processing processor architecture production compilers program compilers
