Conference paper
Capacitor-Free, Low Drop-Out Linear Regulator in a 180 nm CMOS for Hearing Aids
This paper presents a capacitor-free low dropout (LDO) linear regulator based on a new dual loop topology. The regulator utilizes the feedback loops to satisfy the challenges for hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of an off-chip discrete capacitor connected at the output and operates with 0-100 pF capacitive load.
The design has been implemented in a 0.18 µm CMOS process. The proposed regulator has a low component count and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from 1.0 V - 1.4 V supply. A current step load from 250-500 µA with an edge time (rise and fall time) of 1 ns results at ∆Vout of 64 mV with a settling time of 3 µs when CL = 0.
The power supply rejection ratio (PSRR) at 1 kHz is 63 dB.
| Language: | English |
|---|---|
| Publisher: | IEEE |
| Year: | 2016 |
| Pages: | 1-5 |
| Proceedings: | 2016 IEEE Nordic Circuits and Systems Conference |
| ISBN: | 1509010955 , 1509010963 , 9781509010950 and 9781509010967 |
| Types: | Conference paper |
| DOI: | 10.1109/NORCHIP.2016.7792888 |
| ORCIDs: | Llimos Muntal, Pere , Larsen, Dennis Øland and Jørgensen, Ivan Harald Holger |
CMOS integrated circuits CMOS process Capacitance Capacitors LDO linear regulator Logic gates PSRR Regulators Transient response Transistors Voltage control capacitor-free low dropout linear regulator current 250 muA to 500 muA dual loop topology hearing aid device hearing aids integrated circuit design off-chip discrete capacitor power supply rejection ratio system-on-chip system-on-chip integration voltage 0.9 V voltage 1.0 V to 1.4 V voltage 64 mV voltage regulators
