Conference paper
A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems
Department of Informatics and Mathematical Modeling, Technical University of Denmark1
Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark2
Computer Science and Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark3
This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We consider a system with IP-cores, where the TDM-NoC must provide directed virtual circuits - all with the same bandwidth - between all nodes.
This may not be a frequent scenario, but a general platform should provide this capability, and it is an interesting point in the design space to study. The paper presents an FPGA-friendly hardware design, which is simple, fast, and consumes minimal resources. Furthermore, an algorithm to find minimum-period schedules for all-to-all virtual circuits on top of typical physical NoC topologies like 2D-mesh, torus, bidirectional torus, tree, and fat-tree is presented.
The static schedule makes the NoC time-predictable and enables worst-case execution time analysis of communicating real-time tasks.
Language: | English |
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Publisher: | IEEE |
Year: | 2012 |
Pages: | 152-160 |
Proceedings: | 6th ACM/IEEE International Symposium on Networks-on-Chip |
ISBN: | 1467309737 , 9781467309738 , 0769546773 and 9780769546773 |
Types: | Conference paper |
DOI: | 10.1109/NOCS.2012.25 |
ORCIDs: | Schoeberl, Martin and Sparsø, Jens |
2D mesh topology Bandwidth FPGA friendly hardware design Hardware IP networks NoC topology Real time systems Schedules Time division multiplexing all-to-all virtual circuit bidirectional torus topology circuit switched network-on-chip directed virtual circuit fat tree topology field programmable gate arrays minimum period schedule network topology network-on-chip real time systems real-time systems statically scheduled time division multiplexed network-on-chip time division multiplexing