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10 items by relevance
1 Conference paper

Post-placement temperature reduction techniques

Liu, Wei; Nannarelli, Alberto

Design, Automation & Test in Europe Conference & Exhibition (date), 2010 — 2010, pp. 634-637

With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial

Year: 2010

Language: English

More...
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2 Conference paper

Post-placement temperature reduction techniques

Wei Liu; Nannarelli, Alberto; Calimera, Andrea; Macii, Enrico; Poncino, Massimo

2010 Design, Automation&test in Europe Conference&exhibition (date 2010) — 2010, pp. 634-637

With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial

Year: 2010

Language: English

More...
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3 Conference paper

Post-placement temperature reduction techniques

Liu, Wei; Nannarelli, Alberto; Calimera, Andrea; Macii, Enrico; Poncino, Massimo

Proceedings of the Conference on Design, Automation and Test in Europe — 2010, pp. 634-637

With technology scaled to deep submicron era, temperature and temperature gradient have emerged as important design criteria. We propose two post-placement techniques to reduce peak temperature by intelligently allocating whitespace in the hotspots. Both methods are fully compliant with commercial

Year: 2010

Language: English

More...
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4 Journal article

Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization

Liu, Wei; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Nannarelli, Alberto; Poncino, Massimo

I E E E Transactions on Computer - Aided Design of Integrated Circuits and Systems — 2013, Volume 32, Issue 3, pp. 406-418

With the continuing scaling of CMOS technology, on-chip temperature and thermal-induced variations have become a major design concern. To effectively limit the high temperature in a chip equipped with a cost-effective cooling system, thermal specific approaches, besides low power techniques

Year: 2013

Language: English

More...
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