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Conference paper

Multi-physic Analysis for GaN Transistor PCB Layout

From

Department of Electrical Engineering, Technical University of Denmark1

Electronics, Department of Electrical Engineering, Technical University of Denmark2

PCB layout for Gallium Nitride (GaN) transistor power loops are critical for achieving a stable operation in power converters. Optimal design should minimize the parasitic inductance as well as provide a low thermal resistance for heat dissipation. A multi-physic evaluation of performance between different PCB designs are made and a novel layout is proposed in this paper.

The parasitic inductance and heat distribution of each layout are compared. The parasitic inductance is obtained from the oscillation frequency of the transistor drain-source voltage ringing. The thermal comparison is done with a combination of measurements and calculations. To ensure identical operating conditions, the buck converter adopts a modular design idea, where the plug-in totem poles of different designs are placed on the same motherboard.

An optimized strategy for GaN transistor layout is given.

Language: English
Publisher: IEEE
Year: 2019
Pages: 3407-3413
Proceedings: 2019 IEEE Applied Power Electronics Conference and Exposition
ISBN: 1538683296 , 153868330X , 153868330x , 1538683318 , 9781538683293 , 9781538683309 and 9781538683316
ISSN: 10482334 and 24706647
Types: Conference paper
DOI: 10.1109/APEC.2019.8722166
ORCIDs: Sun, Bainan , Jørgensen, Kasper Lüthje , Zhang, Zhe and Andersen, Michael A. E.

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